The present invention relates generally to erasing memory cells of non-volatile memory arrays, and particularly to methods for erasing a bit of a memory cell so as to reduce a drift of threshold voltage thereafter and increasing reliability.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (SRAMs), erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
Memory cells generally comprise transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage (Vt) that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
The act of programming the cell involves charging the floating gate with electrons, which increases the threshold voltage Vt. The act of erasing the cell involves removing electrons from the floating gate, which decreases the threshold voltage Vt.
A binary memory stores one bit of data per memory cell. Accordingly, floating gate transistors in binary memory cells have two distinguishable states, a high threshold voltage state and a low threshold voltage state. A memory cell having a threshold voltage above a cut-off threshold voltage value, referred to as a read reference voltage level, is considered to be in a programed state. Conversely, a memory cell having a threshold voltage below the read reference voltage level is considered to be in an erased state.
It is noted that a multibit-per-cell memory stores multiple bits per memory cell. Accordingly, a range of threshold voltages for a memory cell is divided into a number of states corresponding to the possible multibit data values stored in the memory cell.
A concern in non-volatile semiconductor memory is drift or unintended changes in the threshold voltages of memory cells. For example, over time, charge tends to leak from the floating gates of memory cells and change the threshold voltages of the cells. Charge leakage decreases the threshold voltage of an n-channel memory cell. Alternatively, a floating gate or an insulator surrounding the floating gate can collect or trap charge and increase the threshold voltage of a cell. Further, operation of the memory, for example, programming or erasing, stresses or disturbs memory cells not being accessed and can change threshold voltages. Changes in the threshold voltage are a problem because the state of the memory cell and the data value stored in the memory cell can change and create a data error. Such data errors are intolerable in many memory applications. The problem is worse for multibit-per-cell memories than for binary memories because the range of threshold voltages corresponding to a particular state is typically smaller in a multibit-per-cell memory which makes changes in the state of the memory cell more likely.
Another type of non-volatile cell is a nitride, read only memory (NROM) cell, described in Applicant""s copending U.S. patent application Ser. No. 08/905,286, entitled xe2x80x9cTwo Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d. Programming and erasing of NROM cells are described in Applicant""s copending U.S. patent application Ser. No. 09/730,586, filed Dec. 7, 2000 and entitled xe2x80x9cProgramming And Erasing Methods For An NROM Arrayxe2x80x9d, which is a continuation-in-part application of Applicant""s copending U.S. patent application Ser. No. 09/563,923, filed May 4, 2000 and entitled xe2x80x9cProgramming Of Nonvolatile Memory Cellsxe2x80x9d. The disclosures of all the above-referenced patent documents are incorporated herein by reference.
Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area defines one bit. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) sandwich underneath a gate. When programming a bit, channel hot electrons are injected into the nitride layer. The negative charge raises the threshold voltage of the cell, if read in the reverse direction. For NROM cells, each bit is read in the direction opposite (a xe2x80x9creverse readxe2x80x9d) to that of its programming direction. An explanation of the reverse read process is described in U.S. patent application Ser. No. 08/905,286, mentioned above.
One procedure for erasing bits in NROM cells is described in Applicant""s copending U.S. patent application Ser. No. 09/730,586, mentioned hereinabove. The method comprises applying erase pulses that are adapted to the current state of the memory array. Specifically, this involves measuring the current threshold voltage level of a bit to be erased (the measurement being made with an accuracy within a predetermined range), and selecting an incremental drain voltage level of the next erase pulse, which is to be applied to that bit, in accordance with the measured current threshold voltage level.
The following is an illustrative example of erasing bits in a block of NROM cells, according to the aforementioned method. First, the block to be erased is read and then its erase state is checked. If all of the bits of the block are erased already, the process is finished. If the block requires further erasure, an erase pulse is provided, typically with predefined gate and drain voltages, which may be defined in accordance with any suitable criteria. The read level may then be subsequently decreased from the program verify level (i.e., the level of fully programmed bits) towards the erase verify level (i.e., fully erased) to determine how much erasure has occurred and how much more needs to occur.
Specifically, the read voltage level may be set to the program verify (PV) level and the block is read. If all of the bits of the block pass the read operation, the read voltage level is reduced as long as it has not yet reached the erase verify level. If the read operation is successful at the erase verify level, then the block has been fully erased and the process finishes. However, if the read operation fails at some point, the drain voltage level is increased in accordance with any suitable criteria, and another erase pulse is applied using the new drain voltage level. The erasure process continues until the erase pulses have successfully erased the bits that are required to be erased. The process may comprise checking if the number of erase pulses has not exceeded a maximum. If the maximum has been exceeded, then an error flag may be set and the process may be stopped.
As mentioned hereinabove for non-volatile semiconductor memory cells, a concern with NROM cells is drift or unintended changes in the threshold voltages of memory cells. For example, over time at room temperature, bits that are supposed to be in an erased state may experience an increase in threshold voltage.
There are several problems associated with the drift problem. The drift causes a loss in the margin of voltage level between the erased state voltage level and the read reference level. Accordingly, in the prior art, the erase verify level may be set at a certain low voltage level, taking into account a factor of safety so as to distance the erased state voltage level from the read reference level. This is referred to as maintaining a xe2x80x9cwindowxe2x80x9d between the erased state voltage level and the read reference level. There may be likewise a xe2x80x9cwindowxe2x80x9d between the programmed state voltage level and the read reference level. One way of combating the margin loss would be to maintain a large window that would separate the erased state voltage level from the read reference level even after drift in the erased state voltage level over time. However, this in turn causes other problems. A larger window may lower reliability by detrimentally affecting cycling and retention. In addition, the larger window necessitates longer write times, thereby causing a loss in performance.
The present invention seeks to provide methods for erasing a bit of a memory cell so as to reduce the drift of the threshold voltage thereafter. In accordance with a preferred embodiment of the present invention, an erase pulse is applied to a bit and the bit is read to check if the bit has passed an erase verify level. In contrast to the prior art, if the bit has passed the erase verify level, then at least one more erase pulse is applied to that bit.
The extra erase pulse may be applied with the same voltage levels of gate and drain and for the same time duration as the previous erase pulse. Alternatively, any or all of the values may be changed for the extra pulse.
In accordance with another embodiment of the invention, reliability may be further improved by applying the at least one extra erase pulse only if the bit fails a second verify level, as is described in detail further hereinbelow.
There is thus provided in accordance with a preferred embodiment of the invention a method for erasing a bit of a memory cell in a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.
In accordance with one embodiment of the invention the method includes applying an erase pulse of an equal magnitude as an erase pulse applied to the at least one bit just prior to applying the at least one more erase pulse.
Alternatively, in accordance with another embodiment of the invention, the method includes applying an erase pulse of a lower magnitude than an erase pulse applied to the at least one bit just prior to applying the at least one more erase pulse.
Alternatively, in accordance with yet another embodiment of the invention, the method includes applying an erase pulse of a greater magnitude than an erase pulse applied to the at least one bit just prior to applying the at least one more erase pulse.
In accordance with a preferred embodiment of the invention the applying at least one more erase pulse includes applying an erase pulse for an equal, lower or greater time duration as an erase pulse applied to the at least one bit just prior to applying the at least one more erase pulse.
Further in accordance with a preferred embodiment of the invention the method includes, prior to applying the at least one more erase pulse to the at least one bit, erase verifying the at least one bit with a second erase verify level, the second erase verify level being at a lower voltage level than the first erase verify level or the same.
Still further in accordance with a preferred embodiment of the invention the method includes applying at least one more erase pulse to the at least one bit only if the bit has passed the first erase verify level and failed the second erase verify level.
In accordance with a preferred embodiment of the invention the method further includes, after erase verifying the at least one bit, waiting a period of time prior to applying the at least one more erase pulse to the at least one bit.
In accordance with a preferred embodiment of the invention applying the erase pulse (or the at least one more erase pulse) includes erasing with hot hole injection.
There is also provided in accordance with a preferred embodiment of the invention a non-volatile memory cell array including a plurality of transistor memory cells, a power supply adapted to generate erase pulses to bits of the cells, and a controller in communication with the power supply, the controller adapted to perform the steps of applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.
In accordance with a preferred embodiment of the invention the memory cells include nitride read only memory (NROM) cells.